A semiconductor circuit has been made to show a high performance by high densification achieved by miniaturization of transistor, resistance, wiring and the like constituting a circuit, or simultaneously by high-speed responses. In addition, layering of wirings has enabled higher densification and higher integration. The semiconductor production techniques that have enabled the above include STI (Shallow Trench Isolation), planarization of an interlayer dielectric film, damascene process, and metal plug. STI is one of transistor element isolation, the damascene is one of an embedding technique of metal wiring and the metal plug is one of three-dimensional wiring using a metal having a structure penetrating an interlayer dielectric film. The technique essential for each step is CMP (Chemical Mechanical Polishing), which is constantly used for each step of STI formation, planarization of an interlayer dielectric film, damascene process and metal plug embedding. These fine patterns are formed by transcription of a resist mask formed by a photolithography step. As miniaturization proceeds, the depth of the focus of the projector lens used for the lithography becomes shallow, and the required level of flatness becomes high, since the concaves and convexes on the wafer needs to be smaller than the depth. By planarizing the worked surface by CMP, a flat surface of a nano order or atom level can be obtained, and high performance by three-dimensional wiring, i.e., layering, becomes possible.
In an STI formation step, after formation of a trench to be an element isolation region and formation of a polishing stop film on regions other than the groove, an insulating film for element isolation is formed inside the groove and on the polishing stop film. Then, an excess insulating film is removed by polishing by CMP until the polishing stop film appears, and planarized. As the stop film, silicon nitride is generally used and, as the insulating film, silicon oxide is often used.
For high planarization and element protection, it is necessary to decrease the rate of polishing the stop film and insulating film, when the stop film is exposed. To certainly expose the stop film on the entire surface of a wafer, a region on the wafer where the polishing rate is fast is polished for a comparatively long time even after exposure of the stop film. When the polishing rate of an insulating film is high even after exposure of the stop film, therefore, the insulating film on the concave part, which is an element isolation region (STI region), of the pattern is excessively removed (dishing phenomenon), and the property and reliability of the element decrease.
At present, for STI formation, a slurry containing ceria (cerium oxide) abrasive grain and an anionic polymer in combination is mainly used to achieve high planarization and to suppress polishing when polished excessively (e.g., patent documents 1 and 2). In addition, a system using an anionic polymer, and polyvinylpyrrolidone, a cationic compound and an ampholytic compound in combination is also known (e.g., patent document 3). Furthermore, a system using a low-molecular-weight compound selected from particular amino alcohol, amino carboxylic acid, hydroxycarboxylic acid and the like is also known (e.g., patent documents 4 and 5).